1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, particularly to the layout of a semiconductor integrated circuit device on a semiconductor chip. More particularly, the present invention relates to the layout of a memory device on a chip, and to the bus arrangement and signal transfer timing with respect to the memory device.
2. Description of the Background Art
FIG. 25 is a schematic diagram of an entire structure of a conventional semiconductor integrated circuit device. Referring to FIG. 25, the conventional semiconductor integrated circuit device includes a plurality of bonding pads 1 arranged along the periphery of a semiconductor chip CH, and an internal circuitry region 2 defined by these bonding pads 1. Bonding pads 1 are arranged enclosing internal circuitry region 2 along the four sides of semiconductor chip CH. Bonding pad 1 is electrically connected to an external lead terminal via a bonding wire (not shown), and is electrically coupled with an external device.
In internal circuitry region 2, there are arranged a central processing unit (CPU) 3 executing operational processing, a ROM (read only memory) 4 storing data/instructions required by CPU 3, a RAM (random access memory) 5 storing the data/instruction used by CPU 3, and also serving as a working area of CPU 3 to temporarily store data, and peripheral functions 6 and 7 including an input/output interface, a timer, an asynchronous receiver transmitter unit (UART) and others. Peripheral function 6 is disposed adjacent to CPU 3. Peripheral function 7 is disposed between ROM 4 and RAM 5.
The semiconductor integrated circuit device of FIG. 25 is a so-called one-chip micro computer. By integrating CPU 3, ROM 4 and RAM 5 on a semiconductor chip CH, the bus line interconnecting these CPU 3, ROM 4 and RAM 5 can be formed by on-chip interconnection lines to shorten the length of the bus line, and signal/data can be transferred at high speed with low power consumption. Thus, high speed processing can be achieved with a small occupying area.
A bus line (not shown) between CPU 3, ROM 4 and RAM 5 is an on-chip interconnection line, and the bus width can be made wide enough to allow increase of the data bit width.
In the semiconductor integrated circuit device of FIG. 25, each component is arranged in internal circuitry region 2 with the layout optimized in order to increase the area usage efficiency for minimizing the chip area. In optimizing the arrangement of each component, the interconnection layout of the internal bus is similarly optimized.
In this semiconductor integrated circuit device, the memory capacity of RAM 4 and RAM 5 is set according to the processing contents. When the processing contents are complicated and the amount of processing data is great, the memory capacity of ROM 4 and/or RAM 5 must be increased.
FIG. 26 schematically shows the layout of a semiconductor memory device in the case in which the memory capacity of ROM 4 and RAM 5 is increased. Referring to FIG. 26, the memory capacity of ROM 14 and RAM 15 in internal circuitry region 2 is increased as compared with that of ROM 4 and RAM 5 shown in FIG. 25, and their respective occupying areas are increased. According to the increase of the area of ROM 14 and RAM 15, the layout is modified so as to minimize the area of semiconductor chip CH. Therefore, a peripheral function 17 between ROM 14 and RAM 15 and a peripheral function 16 adjacent to the CPU differ in internal layout from peripheral functions 7 and 6 in the semiconductor integrated circuit device shown in FIG. 25.
Accordingly, the layout of the interconnection lines from the components such as the UART included in these peripheral functions 16 and 17 to pads 1 differs, and the interconnection length is also changed.
As the interconnection line width and interconnection line pitch become smaller in accordance with the miniaturization of elements, the interconnection line capacitance and line resistance as well as the inter-line capacitance will be changed due to a change in interconnection route. Therefore, this change in interconnection route may accompany a circuit portion weak in immunity against a surge, where disconnection is caused when a surge voltage is generated, and the generated surge voltage is transmitted via the inter-line capacitance to exert an adverse effect on the circuit operation. Therefore, in the case where the memory capacity of such ROMs and/or RAMs is to be modified, the reliability of the semiconductor integrated circuit must be sufficiently re-evaluated from the beginning. This evaluation of a semiconductor integrated circuit device is time-consuming, resulting in increased cost.
The length of internal circuitry region 2 in the X direction and/or Y direction will increase in accordance with an increase of area of ROM 14 and RAM 15. Therefore, the coordinates of pads 1 arranged at the periphery of the chip will also differ. Generally a testing jig is employed for evaluating the reliability of a semiconductor integrated circuit device. This jig is electrically connected to the bonding pads (referred to as xe2x80x9cpadsxe2x80x9d hereinafter) 1, and testing is carried out. When the coordinates of pads 1 are altered, the pad contact position of the jig must be modified according to the coordinates of pads 1 of the newly produced semiconductor integrated circuit device. This modification of the jig for re-evaluating semiconductor integrated circuit device requires much time and a great amount of labor, and also increases cost.
Moreover, when the chip area of the semiconductor integrated circuit device is increased to increase a bus line length between components as shown in FIG. 26, the propagation time of signal/data becomes longer. Therefore, in the case where the internal circuitry performs a processing in synchronization with a clock signal and the cycle time of the processing is determined by the clock signal, when the timing between internal control signals and transferred signal/data is deviated, sufficient set up/hold time cannot be ensured and a signal of an intermediate voltage level may be transferred.
If a signal line is maintained at the level of an intermediate potential, through current disadvantageously flows at the next stage circuit, to increase power consumption. Furthermore, data cannot be properly transferred. Particularly, in the case where the next stage circuit is constituted by an MOS transistor (insulated gate type field effect transistor), such a through current would degrade the low power consumption performance which is the feature of an MOS circuit. There is also a possibility of erroneous operation since the next stage circuit cannot be operated properly due to the signal of the intermediate voltage level.
An object of the present invention is to provide a semiconductor integrated circuit device that can suppress layout modification to a minimum when the memory capacity of a memory device is modified.
Another object of the present invention is to provide a semiconductor integrated circuit device that can transfer signal/data at high speed even in the case where the bus line length is increased by layout modification.
A further object of the present invention is to provide a semiconductor integrated circuit device that can transfer signal/data properly at high speed and at low power consumption even in the case where the bus line length is changed by layout modification.
Briefly stated, according to the present invention, a semiconductor chip is divided into a first semiconductor region defined by pads, and a second region outside these pads. At least a part of an ROM and/or RAM is arranged in the second semiconductor region.
Specifically, according to an aspect of the present invention, a semiconductor integrated circuit device includes a first semiconductor region where internal circuitry including a processor is arranged, a second semiconductor region where a first memory device is arranged, and pads arranged between the first and second semiconductor regions.
According to another aspect of the present invention, a semiconductor integrated circuit device includes a processor, first and second memory devices, a select signal generation circuit generating a memory select signal specifying the first and second memory devices according to a memory address signal from the processor, and transmitting the generated memory select signal in synchronization with a first clock signal, a select circuit coupling to an internal bus a memory device specified by the memory select signal out of the first and second memory devices in response to the memory select signal, and a transfer circuit transferring data from the processor to the select circuit via the internal bus in synchronization with a second clock signal complementary to the first clock signal.
By arranging pads between the first and second semiconductor regions and disposing the first memory device in the second semiconductor region, the layout of the first semiconductor region is substantially fixed whereas the layout of the first memory device in the second semiconductor region is modified according to the memory capacity. The layout of the internal circuitry as well as the layout of the internal lines are not changed. Therefore, the characteristics of the internal circuitry can be ensured. Only the labor for modifying the layout of the first memory device and testing thereof is required. Since the coordinates of the pads are not changed, a conventional jig can be used to test the semiconductor integrated circuit device. In the test program, only the address region has to be modified according to the memory capacity of the first memory device. Thus, modification of the memory capacity of a memory device can be easily accommodated for.
Control of the select circuit and data transfer are effected in synchronization with clock signals complementary to each other. Data can be reliably transferred after a select circuit enters a selected state. Therefore, data of a definite state can be reliably transferred to a next stage memory device. Since only the selected memory device is coupled to the memory data bus, the load on the bus is reduced to allow high speed data transfer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.